Is the Problem Checker _too_ smart?

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Chris Knudsen
Posts: 23
Joined: Thu May 14, 2020 9:46 am

Is the Problem Checker _too_ smart?

Post by Chris Knudsen »

My design has an imported step file comprised of a PCB with an Ethernet jack hanging off one edge.

The PCB already has standoffs placed, so I won't be making use of PEM mounts. I only need to align some thru holes on the bottom, and cutouts for the Eth jack and some led's on the back panel.

All is going swimmingly (nice work folks!), except the Problem Checker (which is automatically invoked every time the file is opened), complains about the Eth jack protruding out the back.
oomf.png
oomf.png (21.43 KiB) Viewed 2740 times
Are there any steps to legitimately make this situation pass the checks? It seems like it's probably a common situation.

The design is using the 1U Rackmount template.

-Chris
EtherOuty.png
EtherOuty.png (17.32 KiB) Viewed 2740 times
OutEthery.png
OutEthery.png (45.43 KiB) Viewed 2740 times

Chris Knudsen
Posts: 23
Joined: Thu May 14, 2020 9:46 am

Re: Is the Problem Checker _too_ smart?

Post by Chris Knudsen »

Version: 5.3.28, Win10

Chris Knudsen
Posts: 23
Joined: Thu May 14, 2020 9:46 am

Re: Is the Problem Checker _too_ smart?

Post by Chris Knudsen »

More views of the Eth connector cutout:

Is a 3 mil gap too tight for the Auto-Problem-Checker ;-) ?

00_Ethgap.PNG
00_Ethgap.PNG (23.22 KiB) Viewed 2730 times
01_EthGap.PNG
01_EthGap.PNG (110.98 KiB) Viewed 2730 times
03_EthGap.PNG
03_EthGap.PNG (30.14 KiB) Viewed 2730 times

Chris Knudsen
Posts: 23
Joined: Thu May 14, 2020 9:46 am

Re: Is the Problem Checker _too_ smart?

Post by Chris Knudsen »

I tried to lower the PCB, and made the Eth jack cutout larger (taller).

No change. The checker still complains.
04_Capture.PNG
04_Capture.PNG (34.43 KiB) Viewed 2726 times

mpyne
Site Admin
Posts: 101
Joined: Mon Nov 14, 2016 11:15 am

Re: Is the Problem Checker _too_ smart?

Post by mpyne »

Hello Chris,

I think there is actually no problem. Really looks a like a false positive to me.


What I think is happening is the group the component is in intersects the boundary of profile of the face it is on. This may or may not be an issue depending on whether or not a gap exists between the adjacent face you are planning to add your IO cutouts.

Let me know if you disagree. :D

Matt

Chris Knudsen
Posts: 23
Joined: Thu May 14, 2020 9:46 am

Re: Is the Problem Checker _too_ smart?

Post by Chris Knudsen »

Hi Matt,

The group component was placed on the bottom panel.

The error msg indicates a problem with the back panel. This is confirmed by moving the PCB component away from the back panel (Y-axis), while keeping the Z coord the same. If this is done the error goes away.

This tells me that there is a detected collision with only the back panel.

The only bit that sticks out beyond the PCB edge is the Eth jack. The cutout in the back panel looks to have enough clearance for the Jack.

So yes, I'd agree that it's a false-positive (and it reassures me that you think so as well).

I'll try placing the 3D PCB Step component on the back panel instead. That's a bit of trickier math, but I'll see how it goes.
Last edited by Chris Knudsen on Fri Feb 05, 2021 11:55 am, edited 1 time in total.

Chris Knudsen
Posts: 23
Joined: Thu May 14, 2020 9:46 am

Re: Is the Problem Checker _too_ smart?

Post by Chris Knudsen »

The Problem Check returns happy results when a 3D Step component that has panel-protruding bits, is placed on the same panel as the protruding-bits-cutout.

success.PNG
success.PNG (82.39 KiB) Viewed 2717 times

The moral of the story:
  • When placing a 3D step file, consider which face has elements that need to protrude through a panel.
  • When you go to place the 3D component, switch to the panel that has those protrusions, in order to edit that panel.
  • Place the 3D component on that panel.

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